How to Read From a Memory Location in Verilog

An array declaration of a cyberspace or variable can exist either scalar or vector. Any number of dimensions can exist created by specifying an address range after the identifier name and is called a multi-dimensional array. Arrays are allowed in Verilog for reg, wire, integer and real data types.

                      reg        y1 [11:0];        // y is an scalar reg array of depth=12, each i-scrap wide 	wire [0:7] y2 [3:0]          // y is an eight-flake vector cyberspace with a depth of 4 	reg  [7:0] y3 [0:1][0:3];    // y is a 2D assortment rows=2,cols=4 each eight-bit broad                  

An index for every dimension has to be specified to admission a particular element of an array and tin be an expression of other variables. An assortment can be formed for whatever of the dissimilar data-types supported in Verilog.

Note that a memory of n 1-scrap reg is not the same every bit an due north-flake vector reg.

Assignment

                      y1 = 0; 						// Illegal - All elements can't be assigned in a single become 	 	y2[0] = 8'ha2; 			// Assign 0xa2 to index=0  	y2[2] = 8'h1c; 			// Assign 0x1c to index=two 	y3[1][2] = 8'hdd; 	// Assign 0xdd to rows=1 cols=2 	y3[0][0] = eight'haa; 	// Assign 0xaa to rows=0 cols=0                  

Example

The code shown below simply shows how different arrays tin can be modeled, assigned and accessed. mem1 is an viii-scrap vector, mem2 is an 8-chip array with a depth of four (specified by the range [0:3]) and mem3 is a 16-scrap vector 2nd array with 4 rows and 2 columns. These variables are assigned different values and printed.

                      module des ();   reg [7:0]  mem1; 							// reg vector eight-bit broad   reg [7:0]  mem2 [0:3]; 				// eight-bit wide vector array with depth=4   reg [15:0] mem3 [0:3][0:ane]; 	// sixteen-bit wide vector 2D array with rows=4,cols=2      initial begin     int i;          mem1 = eight'ha9;     $display ("mem1 = 0x%0h", mem1);          mem2[0] = eight'haa;     mem2[ane] = 8'hbb;     mem2[two] = 8'hcc;     mem2[3] = 8'hdd;     for(i = 0; i < iv; i = i+ane) brainstorm       $display("mem2[%0d] = 0x%0h", i, mem2[i]);     stop          for(int i = 0; i < 4; i += i) begin       for(int j = 0; j < 2; j += 1) begin         mem3[i][j] = i + j;         $display("mem3[%0d][%0d] = 0x%0h", i, j, mem3[i][j]);       end     end   end endmodule                  

Simulation Log

ncsim> run mem1 = 0xa9 mem2[0] = 0xaa mem2[one] = 0xbb mem2[2] = 0xcc mem2[iii] = 0xdd mem3[0][0] = 0x0 mem3[0][i] = 0x1 mem3[1][0] = 0x1 mem3[1][1] = 0x2 mem3[2][0] = 0x2 mem3[2][1] = 0x3 mem3[3][0] = 0x3 mem3[3][1] = 0x4 ncsim: *W,RNQUIE: Simulation is complete.        

Memories

Memories are digital storage elements that help store a data and information in digital circuits. RAMs and ROMs are good examples of such memory elements. Storage elements can be modeled using 1-dimensional arrays of blazon reg and is chosen a memory. Each element in the retentivity may correspond a word and is referenced using a unmarried array index.

Register Vector

Verilog vectors are alleged using a size range on the left side of the variable name and these go realized into flops that match the size of the variable. In the code shown beneath, the design module accepts clock, reset and some control signals to read and write into the block.

It contains a 16-bit storage element chosen register which simply gets updated during writes and returns the current value during reads. The register is written when sel and wr are loftier on the aforementioned clock edge. Information technology returns the electric current data when sel is high and wr is depression.

                      module des (    input           clk,                 input           rstn,                 input           wr,                 input           sel,                 input [15:0]    wdata,                 output [15:0]   rdata);  	reg [xv:0] register;  	always @ (posedge clk) brainstorm     if (!rstn)     	register <= 0;     else begin     	if (sel & wr)        	register <= wdata;     	else       	register <= register;     cease 	stop  	assign rdata = (sel & ~wr) ? register : 0; endmodule                  

The hardware schematic shows that a 16-bit flop is updated when command logic for writes are agile and the current value is returned when control logic is configured for reads.

Array

In this example, register is an array that has four locations with each having a width of xvi-$.25. The design module accepts an additional input indicate which is called addr to admission a particular index in the array.

                      module des (    input           clk,                 input           rstn,                 input  [one:0]    addr,                 input           wr,                 input           sel,                 input [15:0]    wdata,                 output [15:0]   rdata);  reg [15:0] register [0:3]; integer i;  always @ (posedge clk) brainstorm     if (!rstn) brainstorm         for (i = 0; i < four; i = i+1) begin              register[i] <= 0;         end     cease else begin         if (sel & wr)              register[addr] <= wdata;         else             register[addr] <= annals[addr];     end end   assign rdata = (sel & ~wr) ? annals[addr] : 0; endmodule                  

It tin be seen in the hardware schematic that each index of the assortment is a 16-bit bomb and the input address is used to access a particular set of flops.

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Source: https://www.chipverify.com/verilog/verilog-arrays

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